Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.
Technical notePower semiconductorsEven after AI racks move to high-voltage DC distribution, a low-voltage, high-current conversion stage remains just ahead of the GPU. This Technical Note looks at moving that stage closer to the load as a cooling-structure problem. The full report is available in Korean. An English summary is provided on this page.
Technical noteThermal controlThis Technical Note addresses the warpage and component tilt that arise when copper posts and MLCCs mounted together on a wafer are reflowed in one laser step. It describes a process that uses a light-transmitting upper head to support the parts and remove heat.
Technical noteThermal controlThis Technical Note examines how warpage left after molding disturbs solder ball mounting and board-level joints in fine-pitch FCCSP. It describes a process that restores flatness outside the mold through reheating, pressing and constrained cooling.
Technical notePackagingThis Technical Note addresses the thermal exposure that arises when a logic die is bonded in an Intel EMIB-T package. It describes a process that keeps bonding pressure in place while moving heat generation to the joints, and proposes a joint feasibility program with Intel. The attached Technical Note is in English.
Technical noteCPOThis Technical Note addresses the two places where heat becomes a problem in co-packaged optics: the EIC–PIC bonding process and the thermo-optic tuners inside the PIC. It describes how the heat path is designed for each location. The full report is available in Korean. An English summary is provided on this page.
Technical noteThermal controlIn a COUPE structure, the heat is needed at the bonding interface between the EIC and the PIC. Oven annealing instead puts heat into the entire assembly, including the support silicon and the optical devices. This technical note sets out what that difference changes in a structure whose optical paths and coupling alignment are sensitive to heat. The full report is available in Korean. An English summary is provided on this page.
Technical noteHBMAs HBM stacks reach 12 layers, the dies get thinner and the number of interfaces grows. Bonding and annealing layer by layer, or stacking the dielectric first and annealing the whole assembly in an oven, both put the entire stack through a thermal history. This technical note describes a process that fixes all 12 layers by dielectric bonding first and completes the copper joins in a single 1500 nm photothermal exposure. The full report is available in Korean. An English summary is provided on this page.
BriefThermal controlAdvanced packaging demands a fast reaction at the bond interface while allowing an ever lower thermal budget for the structures around it. The two demands conflict. Instead of heating and cooling the whole assembly, this brief sets out an approach that switches where energy couples in space and time, applied to two processes: HBM bonding and CPO integration.
Technical noteThermal controlHybrid bonding heats an entire wafer for 0.5 to 4 hours to complete the Cu bond, even though the heat is needed only within a few micrometres of the interface. This technical note sets out an approach that transmits 1500 nm light through the silicon substrate and generates heat for nanoseconds only in an absorbing layer behind the Cu pad, together with the reasoning behind the design.