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Hybrid bonding heats an entire wafer for 0.5 to 4 hours to complete the Cu bond, even though the heat is needed only within a few micrometres of the interface. This technical note sets out an approach that transmits 1500 nm light through the silicon substrate and generates heat for nanoseconds only in an absorbing layer behind the Cu pad, together with the reasoning behind the design.
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Summary
Hybrid bonding heats an entire wafer for 0.5 to 4 hours to complete the Cu bond, even though the heat is needed only within a few micrometres of the interface. Light at 1500 nm sits in a band where interband absorption in silicon is suppressed, so it passes through the substrate and turns into heat for nanoseconds only in a thin absorbing layer behind the pad. The approach changes where and for how long heat is applied rather than how hot the interface gets. Twenty-five appendix items carry the calculations for thermal diffusion depth, required energy, recess closure and cooling rate, along with the conditions for PIC-EIC demonstration.
Conclusion
The difference in this technology is not the temperature but where and for how long heat is applied. Oven annealing holds an entire wafer at 150-300 °C for 0.5 to 4 hours and thermocompression heats a whole die for seconds to tens of seconds, whereas here only the absorbing layer behind the pad is heated for 20-200 ns (design value). Holding the peak interface temperature equal, the ratio of one-dimensional thermal diffusion depth between a 20 ns pulse and 1 ms of continuous heating is about 220 (calculated). That heat is generated and that a metallurgical bond is completed are two different things. The Cu diffusion distance under a single nanosecond pulse is on the scale of a few atomic layers, and the primary driver of recess closure is the instantaneous thermal expansion of constrained Cu. The present stage is securing an analysis-based design window; the temperature at which bonding is established and the ablation threshold are design assumptions and belong to the PoC decision criteria. The entry path is thermal budget reduction, leaving the existing process sequence and pad structure in place and starting by relaxing the annealing conditions, extending to full replacement where room-temperature dielectric bond strength is sufficient. PIC-EIC is the first demonstration case. Photonic chips are already designed to operate in the 1550 nm band, which makes securing the optical path easier; BEOL low-k dielectrics set the thermal budget limit; and waveguide coupling alignment is the most demanding at sub-micron level, so bond resistance, strength, optical loss and alignment can all be verified on a single specimen.
Topics
- Thermal control
- Packaging
