Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.
Technical noteGlass substratesThis Technical Note sets out how to test the durability of interconnects and interfaces in copper-filled through-glass vias with double-sided wiring. It centers on IST and solder float and also covers reflow, thermal cycling, temperature-humidity testing and failure analysis.
Technical notePlatingThis Technical Note examines the burden that sputtered seed layers place on large-area RDL built on panels, as in CoPoS. It describes a wet metallization approach that changes only the seed-forming module, using a PDA interface layer and electroless copper.
Technical noteThermal controlThis Technical Note addresses the warpage and component tilt that arise when copper posts and MLCCs mounted together on a wafer are reflowed in one laser step. It describes a process that uses a light-transmitting upper head to support the parts and remove heat.
Technical noteBonding materialsThis Technical Note sets out a process design for making Cu/PDA particles for copper sintering pastes used in power semiconductor die attach, running from acid pickling to seed growth in one wet process. It also describes how each step is to be verified. The full report is available in Korean. An English summary is provided on this page.
Technical noteThermal controlThis Technical Note examines how warpage left after molding disturbs solder ball mounting and board-level joints in fine-pitch FCCSP. It describes a process that restores flatness outside the mold through reheating, pressing and constrained cooling.
Technical notePackagingThis Technical Note addresses the thermal exposure that arises when a logic die is bonded in an Intel EMIB-T package. It describes a process that keeps bonding pressure in place while moving heat generation to the joints, and proposes a joint feasibility program with Intel. The attached Technical Note is in English.
Technical noteHBMAs HBM stacks reach 12 layers, the dies get thinner and the number of interfaces grows. Bonding and annealing layer by layer, or stacking the dielectric first and annealing the whole assembly in an oven, both put the entire stack through a thermal history. This technical note describes a process that fixes all 12 layers by dielectric bonding first and completes the copper joins in a single 1500 nm photothermal exposure. The full report is available in Korean. An English summary is provided on this page.
BriefPackagingPlacing several GPU dies and multiple HBM stacks on a single interposer is driving package area up sharply. The moment the area grows, warpage moves to the front of the bonding process. This brief sets out how constraining the package shape and cutting heating and cooling time fit together.
BriefThermal controlAdvanced packaging demands a fast reaction at the bond interface while allowing an ever lower thermal budget for the structures around it. The two demands conflict. Instead of heating and cooling the whole assembly, this brief sets out an approach that switches where energy couples in space and time, applied to two processes: HBM bonding and CPO integration.