Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.
Technical notePlatingThis Technical Note examines why copper plating slows down in deep through-glass vias from the standpoint of ion supply, and sets out a development concept that uses nitrogen nanobubbles to replace the liquid inside the via, together with a staged verification plan. The full report is available in Korean. An English summary is provided on this page.
ReportSolarThis report explains a transparent perovskite solar cell that replaces ITO on both electrodes with continuous ultra-thin metal films, together with the wet, low-temperature process used to make the electrodes and the fields where the cell can be applied. The full report is available in Korean. An English summary is provided on this page.
Technical notePackagingThis Technical Note addresses the thermal exposure that arises when a logic die is bonded in an Intel EMIB-T package. It describes a process that keeps bonding pressure in place while moving heat generation to the joints, and proposes a joint feasibility program with Intel. The attached Technical Note is in English.
Technical noteCPOThis Technical Note addresses the two places where heat becomes a problem in co-packaged optics: the EIC–PIC bonding process and the thermo-optic tuners inside the PIC. It describes how the heat path is designed for each location. The full report is available in Korean. An English summary is provided on this page.
Technical noteEquipment partsThis Technical Note describes a manufacturing platform for semiconductor chamber parts such as focus rings and edge rings, in which a reaction-filled SiC core and a precursor-derived SiC functional layer take on separate roles. It covers the design principles, the process flow and the evaluation plan. The full report is available in Korean. An English summary is provided on this page.
Technical notePlatingThis Technical Note explains how acoustic excitation changes ion supply inside high-aspect-ratio through-glass vias during copper electroplating, and how the apparatus, operating conditions and evaluation method are set up. The full report is available in Korean. An English summary is provided on this page.
Technical noteThermal controlIn a COUPE structure, the heat is needed at the bonding interface between the EIC and the PIC. Oven annealing instead puts heat into the entire assembly, including the support silicon and the optical devices. This technical note sets out what that difference changes in a structure whose optical paths and coupling alignment are sensitive to heat. The full report is available in Korean. An English summary is provided on this page.
Technical noteHBMAs HBM stacks reach 12 layers, the dies get thinner and the number of interfaces grows. Bonding and annealing layer by layer, or stacking the dielectric first and annealing the whole assembly in an oven, both put the entire stack through a thermal history. This technical note describes a process that fixes all 12 layers by dielectric bonding first and completes the copper joins in a single 1500 nm photothermal exposure. The full report is available in Korean. An English summary is provided on this page.
BriefPackagingPlacing several GPU dies and multiple HBM stacks on a single interposer is driving package area up sharply. The moment the area grows, warpage moves to the front of the bonding process. This brief sets out how constraining the package shape and cutting heating and cooling time fit together.