Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.
Technical notePlatingIn vias with aspect ratios of 10:1 and above, conventional sputtering leaves the seed broken on the deep sidewalls. This Technical Note describes a process that extends the sputtered seed at the via entrance down the PDA-coated wall by electrolytic growth.
Technical noteGlass substratesThis Technical Note describes how a functionalized silsesquioxane (SQ) coating can serve as the interface for forming copper in glass vias, RDL layers and on ABF substrates, and which process module changes in each application. The full report is available in Korean. An English summary is provided on this page.
Technical notePlatingThis Technical Note examines the burden that sputtered seed layers place on large-area RDL built on panels, as in CoPoS. It describes a wet metallization approach that changes only the seed-forming module, using a PDA interface layer and electroless copper.
Technical noteThermal controlThis Technical Note addresses the warpage and component tilt that arise when copper posts and MLCCs mounted together on a wafer are reflowed in one laser step. It describes a process that uses a light-transmitting upper head to support the parts and remove heat.
Technical notePlatingThis Technical Note describes how to remove the adhesive-opening step from bottom-up plating of through-glass vias that use a copper foil as the via-bottom electrode. It covers PDA bonding, a pressed electrode, a sealing jig and the plating bath layout.
Technical noteThermal controlThis Technical Note examines how warpage left after molding disturbs solder ball mounting and board-level joints in fine-pitch FCCSP. It describes a process that restores flatness outside the mold through reheating, pressing and constrained cooling.
Technical notePlatingThis Technical Note examines why copper plating slows down in deep through-glass vias from the standpoint of ion supply, and sets out a development concept that uses nitrogen nanobubbles to replace the liquid inside the via, together with a staged verification plan. The full report is available in Korean. An English summary is provided on this page.
Technical notePackagingThis Technical Note addresses the thermal exposure that arises when a logic die is bonded in an Intel EMIB-T package. It describes a process that keeps bonding pressure in place while moving heat generation to the joints, and proposes a joint feasibility program with Intel. The attached Technical Note is in English.
Technical notePlatingThis Technical Note explains how acoustic excitation changes ion supply inside high-aspect-ratio through-glass vias during copper electroplating, and how the apparatus, operating conditions and evaluation method are set up. The full report is available in Korean. An English summary is provided on this page.