Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.
Technical notePrinted electronicsThis Technical Note addresses how roughening for adhesion raises high-frequency conductor loss on the low-loss PTFE and LCP substrates used for smartphone RF feed lines and antennas. It describes smooth metallization that bonds copper through a PDA interface instead of roughening.
Technical notePrinted electronicsThis Technical Note describes printing a PDA pattern on the substrate first so that only the places that need circuitry become adhesion and metallization areas. It sets out the two metallization routes, electroless plating and paste printing, that branch from the same PDA pattern.
Technical noteGlass substratesThis Technical Note examines filling the via cores of glass core substrates by copper paste filling and sintering instead of electrolytic copper growth. It describes a design that uses PDA separately on copper particles and on the via wall, and the resulting manufacturing process.
Technical noteGlass substratesFor electroless copper on metal-oxide adhesion layers used in through-glass via metallization, this Technical Note reviews papers and patents on the internal defects of the copper seed and the effects of heat treatment, which must be checked separately from adhesion to glass.
Technical notePlatingBubbles cling to the walls of blind vias when they are filled with solution and when the solution is exchanged by nanoflushing. This Technical Note explains the problem through the hydrophilicity of PDA-coated surfaces and the way bubbles detach from them.
Technical notePower semiconductorsInP and Ga₂O₃ share two constraints: low thermal conductivity and costly single-crystal substrates. This Technical Note describes a common manufacturing platform that transfers only the functional layer onto a reaction-bonded silicon carbide (RBSC) support and joins it by interface-selective optical heating. The full report is available in Korean. An English summary is provided on this page.
Technical notePlatingIn vias with aspect ratios of 10:1 and above, conventional sputtering leaves the seed broken on the deep sidewalls. This Technical Note describes a process that extends the sputtered seed at the via entrance down the PDA-coated wall by electrolytic growth.
Technical notePhotonicsIn heterogeneous silicon photonics integration, each added material exposes heat-sensitive optical devices to the bonding temperature again. This Technical Note sets out the principle, process and equipment of interface-selective bonding, which converts light into heat only at the designed bond interface. The full report is available in Korean. An English summary is provided on this page.
Technical noteGlass substratesThis Technical Note describes how a functionalized silsesquioxane (SQ) coating can serve as the interface for forming copper in glass vias, RDL layers and on ABF substrates, and which process module changes in each application. The full report is available in Korean. An English summary is provided on this page.