Insights

Reports, briefs and technical notes from Cools on semiconductor packaging technology and industry.

35 results

Newest

검은 배경 위에 쿨스 로고와 TECHNICAL NOTE 라벨, 흰색 큰 글씨로 III-V PV GLASS가 적힌 썸네일.

Single-crystal III–V power-generating glass with transmittance and output set by layer thickness

Semi-transparent solar cells divide a single absorber between daylighting and power generation. This Technical Note describes a manufacturing approach in which the thickness of a single-crystal III–V layer, set by the exfoliation depth, fixes both transmittance and output as product specifications. The full report is available in Korean. An English summary is provided on this page.

October 15, 2026

Concept image looking down at an angle on a large package panel with repeated copper wiring patterns, against a dark navy background.

Technical notePlating

Sputter-free panel-level RDL seed layers by PDA wet metallization

This Technical Note examines the burden that sputtered seed layers place on large-area RDL built on panels, as in CoPoS. It describes a wet metallization approach that changes only the seed-forming module, using a PDA interface layer and electroless copper.

October 13, 2026

검은 배경에 쿨스 로고와 TECHNICAL NOTE 라벨, 흰색 대형 글자로 800V POWER TILE이 적힌 테크니컬 노트 썸네일.

Technical notePower semiconductors

Power conversion after 800 V distribution and double-sided direct cooling

Even after AI racks move to high-voltage DC distribution, a low-voltage, high-current conversion stage remains just ahead of the GPU. This Technical Note looks at moving that stage closer to the load as a cooling-structure problem. The full report is available in Korean. An English summary is provided on this page.

October 13, 2026

Concept image of a red laser from an overhead source passing through a transparent disc head onto a wafer densely populated with copper posts and components, against a dark navy background.

Technical noteThermal control

Laser reflow for WLP with a light-transmitting head that holds parts and draws off heat

This Technical Note addresses the warpage and component tilt that arise when copper posts and MLCCs mounted together on a wafer are reflowed in one laser step. It describes a process that uses a light-transmitting upper head to support the parts and remove heat.

October 12, 2026

Concept image of a transparent glass plate densely drilled with vias descending onto a metal jig topped with copper foil, against a dark teal background.

Technical notePlating

Ashing-free bottom-up filling of through-glass vias with PDA bonding and a pressed electrode

This Technical Note describes how to remove the adhesive-opening step from bottom-up plating of through-glass vias that use a copper foil as the via-bottom electrode. It covers PDA bonding, a pressed electrode, a sealing jig and the plating bath layout.

October 11, 2026

검은 배경 위에 쿨스 로고와 TECHNICAL NOTE 라벨, 흰색 큰 글씨로 CU/PDA PARTICLE이 적힌 썸네일.

Technical noteBonding materials

A single wet process for making Cu/PDA particles for power semiconductor die attach

This Technical Note sets out a process design for making Cu/PDA particles for copper sintering pastes used in power semiconductor die attach, running from acid pickling to seed growth in one wet process. It also describes how each step is to be verified. The full report is available in Korean. An English summary is provided on this page.

October 11, 2026

FCCSP packages with metal lids lined up on a bright production line, with a processing head pressing down on one package in the background and solder balls visible under the package in front.

Technical noteThermal control

An out-of-mold Thermal Clutch process for FCCSP flatness right after molding

This Technical Note examines how warpage left after molding disturbs solder ball mounting and board-level joints in fine-pitch FCCSP. It describes a process that restores flatness outside the mold through reheating, pressing and constrained cooling.

October 10, 2026

검은 배경 위에 쿨스 로고와 TECHNICAL NOTE 라벨, 흰색 큰 글씨의 NANO-FLUSHING이 놓인 테크니컬 노트 썸네일.

Technical notePlating

Nanobubble flushing that renews copper ion supply inside deep vias

This Technical Note examines why copper plating slows down in deep through-glass vias from the standpoint of ion supply, and sets out a development concept that uses nitrogen nanobubbles to replace the liquid inside the via, together with a staged verification plan. The full report is available in Korean. An English summary is provided on this page.

October 9, 2026

남색 배경의 패키지 단면 개념도. 위쪽 사각 광원에서 붉은 빛이 투명한 파란 헤드를 지나 로직 다이 아래 접합부만 주황색으로 빛나고, 오른쪽 HBM 적층은 빛 밖에 있다.

Technical notePackaging

1470 nm selective bonding for Intel EMIB-T

This Technical Note addresses the thermal exposure that arises when a logic die is bonded in an Intel EMIB-T package. It describes a process that keeps bonding pressure in place while moving heat generation to the joints, and proposes a joint feasibility program with Intel. The attached Technical Note is in English.

October 6, 2026